Procedures and Tests for Latency Shifting

Introduction

This page aims at summarizing the procedures and validation steps that need to be followed every time the latency is changed for ATLAS. A first table summarizes in general what to do for latency increases/reductions for the different systems. A second table lists the settings for typical latency configurations.

General Instructions

System Increasing Latency Reducing Latency Validation Procedure
My System Explain here exactly what to do to increase the latency, e.g. +1 BC Explain here exactly what to do to decrease the latency, e.g. -1 BC List the tests to perform in order to make sure that the latency settings were correctly changed. If you have a documented procedure already, it's sufficient to link it here.
CTP Procedure to change the latency    
MUCTPI see CTP    
L1 Calo See the L1Calo latency changing procedure. Check PPM ADC max timeslice=2 in tier0 histograms
L1 Topo Synchronised with L1Calo
IBL Procedure same as Pixel, but for crate I1    
Pix Latency increase by +n BC: Reduce TimTriggerDelay by n BC for Crates B1-B3, L1-L4, D1 and D2 Latency reduction by n BC -> Increase TimTriggerDelay by +n BC for all Pixel crates During data taking (local or ATLAS), check that the expected TimTriggerDelay is published to IS (e.g. in RodMon). Final validation by data taking with HV and preamps on: check cluster size and for hits on track
BCM If ATLAS increases the latency by +n BCID then the BCM InhibitDelay has to be chenged by +n BCID and the BCM L1ATriggerDelay has to be changed by -n BCID. The delays need to be set in the segment BCM_Next_ROD_Module.data.xml for both RODs. Instructions on how to change the segment are in https://twiki.cern.ch/twiki/bin/view/Atlas/BcmShifterInstructionRun2. If ATLAS increases the latency by -n BCID then the BCM InhibitDelay has to be chenged by -n BCID and the BCM L1ATriggerDelay has to be changed by +n BCID. Check that the BCM OHP timing histograms (like the HG channels pulse positions) are filled when there are collisions.
SCT If ATLAS increase the latency 1BC, SCT must reduce TIM delay by 1BC for all 8 DAQ crates. The procedure is following: source /det/sct/tdaq-05-05-00/setup.SCTPhysics01.sh; runjava sctutils/CommitTimDelay coarse=X where X is the new desired Tim delay in clock ticks (an absolute value, not relative). If ATLAS reduce the latency 1BC, SCT must increase TIM delay by 1BC for all 8 DAQ crates. The most proper validatiion is tocheck hits on track or hit efficiency with cosmic or physics runs
TRT To increase latency, you add to the global TDM delay in the COOL database. Instructions can be found at http://twiki.cern.ch/twiki/bin/view/Atlas/TrtTriggerLatency. To decrease latency, you subtract from the TDM delay in COOL database. Instructions can be found at http://twiki.cern.ch/twiki/bin/view/Atlas/TrtTriggerLatency. To validate that the changes work, take a cosmic run with FastOR on, and check that you see tracks in the event display.
LAr The change of the LAr latency can ONLY be performed by a LAr run coordinator or by a LAr software oncall under the supervision of a LAr run coordinator. The procedure is explained here, A change in the bucket setting (CTP) may be needed as well. It is done at initial state. It changes the parameter L1 latency [L1alatency], located in the global parameter panel present in the LAr panel in the run control. The parameter is changed and the data are uploaded and save in the db. To increase the latency add to the value. To reduce the latency subtract from the value. The validation test is first to swap the global parameter page to retrieve the parameters in the DB and make sure that the change has been properly uploaded. Then after the start of run, to look at the position of the physics pulse and make sure that its position remains unchanged after the change in the ctp and the corresponding change in the LAr system.
Tile Set from CTP in the ATLAS partition OKS. Please call CTP. Set from CTP in the ATLAS partition OKS. Please call CTP. Link to Tile Experts Manual.
CSC Done automatically using the global latency value, no expert action. For details: Link to CSC Experts Manual.   Checking done using cluster timing plot
MDT A change in the oracle DB MdtConfigDb is required from the experts, afterwards all MDT chambers need to be re-initialised. MDT expert description   Checking done using individual TDC spectra (e.g. BOL1A13-ML1)
RPC A change in a configuration file is needed, which then gets uploaded to all pads. Procedure to change RPC latency.   Check readout plot, gaussian shoud be centered at BC 3 (out of 8)
TGC Done automatically using the global latency value, no expert action.   Check if there is no ERS message from TGC-RCD mentioning about BCID mismatch for the readout. For the trigger, check DQ plot, SectorLogicBC distribution should show majority events at the current BC
MMEGA      
Lucid Lucid TDAQ is not affected by changes in the trigger latency, since we send no data to the ROS and issue no busy. However, the orbit is used to define the position of BCID 0. As a consequence, to get the luminosity in the right BCID, the oks parameters ChOrbitDelay and LumatOrbitDelay in the PMT(FIB)-SideA(C) objects of class ReadoutModuleLucrod in file LUCID_ROD.segment.xml have to be changed by the same amount and direction as the orbit shift    
ZDC Add 1 to baselinePointer in ZDC COOL folder ReadoutConfig Subtract 1 from baselinePointer in ZDC COOL folder ReadoutConfig  
ALFA      

Standard Settings

This configuration corresponds to a total latency of ???.

System Settings
My System List here values to set in OKS or other databases, configuration files, etc...
CTP  
MUCTPI  
L1 Calo baselinePointer=63 in COOL folder /TRIGGER/L1Calo/V2/Configuration/ReadoutConfig
L1 Topo synchronized with L1Calo
IBL 122 (1 BC readout window)
Pix 122, 17 for B-Layer (1BC readout window)
BCM  
SCT We have a total latency window of 132 ticks. Normally setting is Tim delay = 12
TRT Check Twiki for value: http://twiki.cern.ch/twiki/bin/view/Atlas/TrtTriggerLatency#Run_2
LAr 104 (simple: 4 complex: 9/351)
Tile TileDigiTTCModule, pipeline value: TileLBA_DigiTTCModule = 108, TileLBC_DigiTTCModule = 109, TileEBA_DigiTTCModule = 106, TileEBC_DigiTTCModule = 107. TileTMDBModule, pipeline values: TileEBA_TMDB* = 72, TileEBC_TMDB* = 73.
CSC 127
MDT not a global parameter for MDT, the latency settings are individual for each chamber
RPC  
TGC  
MMEGA  
Lucid  
ZDC  
ALFA  

Specific Settings for ALFA

Today this configuration corresponds to a total latency of 84 BC.

System Settings
My System List here values to set in OKS or other databases, configuration files, etc...
CTP  
MUCTPI  
L1 Calo baselinePointer=71 in COOL folder /TRIGGER/L1Calo/V2/Configuration/ReadoutConfig
L1 Topo Synchronised with L1Calo
IBL 114 (1BC readout)
Pix 114, 9 for B-Layer (1BC readout)
BCM  
SCT Tim delay=4
TRT Check Twiki for value: http://twiki.cern.ch/twiki/bin/view/Atlas/TrtTriggerLatency#Run_2
LAr 112 (simple: 4 complex: 7/351)
Tile TileDigiTTCModule, pipeline values: TileLBA_DigiTTCModule = 116, TileLBC_DigiTTCModule = 117, TileEBA_DigiTTCModule = 114, TileEBC_DigiTTCModule = 115. TileTMDBModule, pipeline values: TileEBA_TMDB* = 80, TileEBC_TMDB* = 81.
CSC 126 for physics
MDT not a global parameter for MDT, the latency settings are individual for each chamber
RPC  
TGC  
MMEGA  
Lucid  
ZDC  
ALFA  
-- Main.glehmann - 2015-07-26
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Topic revision: r32 - 2018-06-26 - gucchiel_40CERN_2eCH
 
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